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1 fn6665.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2008, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. isl62381, isl62382, is l62383, isl62381c, isl62382c, isl62383c high-efficiency, quad or triple-output system power supply controller for notebook computers the isl62381, isl62382, isl62383, isl62381c, isl62382c and isl62383c family of controllers generate supply voltages for battery-powered systems. th ese controllers include two pulse-width modulation (pwm) controllers, adjustable from 0.6v to 5.5v, and two linear regulators, ldo5 and ldo3, that generate a fixed 5v and an adju stable output respectively, and each can deliver up to 100ma. the isl62383 and isl62383c have the same outputs as the isl62381, isl62382, isl62381c and isl62382c but without ldo3 linear regulator. the channel 2 switching regulator will automati cally take over the ldo5 load when programmed to 5v output. this provides a large power savings and boosts efficiency. these controllers include on- board power-up sequencing, two power-good (pgood) outputs, digital soft-start, and inte rnal soft-stop output discharge that prevent negative voltages on shutdown. the patented r 3 pwm control scheme provides a low jitter system with fast response to load transients. light-load efficiency is improved with period-stretching discontinuous conduction mode (dcm) operation. to eliminate noise in audio frequency applications, an ultrasonic dcm mode is included, which limits the minimum switching frequency to approximately 28khz. the isl62381, isl62382, isl62381c and isl62382c are available in a 32 ld 5x5 tqfn package, and the isl62383 and isl62383c are available in a 28 ld 4x4 tqfn package. this family of controllers can operate over the extended temperature range (-10c to +100c). features ? high performance r 3 technology ? fast transient response ? 1% output voltage accuracy: -10c to +100c ? two fully programmable switch-mode power supplies with independent operation ? programmable switching frequency ? integrated mosfet driv ers and bootstrap diode ? adjustable (+1.2v to +5v) ldo output ? fixed +5v ldo output with automatic switchover to smps2 ? internal soft-start and soft-stop output discharge ? wide input voltage range: +5.5v to +25v ? full and ultrasonic pulse-skipping mode ? power-good indicator ? overvoltage, undervoltage and overcurrent protection ? fault identification by pg ood pull-down resistance ? thermal monitor and protection ? pb-free (rohs compliant) applications ? notebook and sub-notebook computers ? pdas and mobile communication devices ? 3-cell and 4-cell li+ battery-powered devices ? general purpose switching buck regulators ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl62381hrtz 62381 hrtz -10 to +100 32 ld 5x5 tqfn l32.5x5a isl62382hrtz 62382 hrtz -10 to +100 32 ld 5x5 tqfn l32.5x5a isl62383hrtz 623 83hrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 isl62381chrtz 62381 chrtz -10 to +100 32 ld 5x5 tqfn l32.5x5a isl62382chrtz 62382 chrtz -10 to +100 32 ld 5x5 tqfn l32.5x5a ISL62383CHRTZ 62383 chrtz -10 to +100 28 ld 4x4 tqfn l28.4x4 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pa ckaged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 term ination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free produc ts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (m sl), please see device information page for isl62381 , isl62382 , isl62383 , isl62381c , isl62382c , isl62383c . for more information on msl please see techbrief tb363 . data sheet may 13, 2011
2 fn6665.5 may 13, 2011 pinouts isl62381, isl62382, isl62381c, isl62382c (32 ld tqfn) top view isl62383, isl62383c (28 ld tqfn) top view fb2 vout2 isen2 ocset2 en2 phase2 ugate2 boot2 fb1 vout1 isen1 oscet1 en1 phase1 ugate1 boot1 pgood2 fset2 fccm vcc2 vcc1 ldo3en fset1 pgood1 lgate2 pgnd ldo5 vin ldo3in ldo3 ldo3fb lgate1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 gnd fb2 vout2 isen2 oscet2 en2 phase2 ugate2 fb1 vout1 isen1 ocset1 en1 phase1 ugate1 pgood2 fset2 fccm vcc2 vcc1 fset1 pgood1 boot2 lgate2 pgnd ldo5 vin lgate1 boot1 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
3 fn6665.5 may 13, 2011 absolute maximum rati ngs thermal information vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v vcc 1,2 , pgood 1,2 , ldo5 to gnd. . . . . . . . . . . . . . -0.3v to +7.0v en 1,2 , ldo3en . . . . . . . . . . . . . . . . . . -0.3v to gnd, vcc1 + 0.3v vout 1,2 , fb 1,2 , ldo3fb, fset 1,2 . . -0.3v to gnd, vcc1 + 0.3v phase 1,2 to gnd . . . . . . . . . . . . . . . . . . . . . . . (dc) -0.3v to +28v (<100ns pulse width, 10j) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0v boot 1,2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot 1,2 to phase 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v ugate 1,2 . . . . . . . . . . . (dc) -0.3v to phase 1,2 , boot 1,2 + 0.3v (<200ns pulse width, 20j) . . . . . . . . . . . . . . . . . . . . . . . . -4.0v lgate 1,2 . . . . . . . . . . . . . . . . . . . (dc) -0.3v to gnd, vcc1 + 0.3v (<100ns pulse width, 4j) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v ldo3, ldo5 output continuous current . . . . . . . . . . . . . . +100ma thermal resistance (typical, notes 4, 5) ja (c/w) jc (c/w) 32 ld tqfn package . . . . . . . . . . . . . 30 1.75 28 ld tqfn package . . . . . . . . . . . . . 37 3 junction temperature range. . . . . . . . . . . . . . . . . .-55c to +150 c operating temperature range . . . . . . . . . . . . . . . .-10 c to +100 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range. . . . . . . . . . . . . . . . . .-10c to +100c supply voltage (vin to gnd) . . . . . . . . . . . . . . . . . . . . 5.5v to 25v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise noted. typical values are at t a =+25c, vin = 12v. boldface limits apply over the operating temperature range, -10c to +100c. parameter conditions min (note 8) typ max (note 8) units vin vin power-on reset (por) rising threshold 5.3 5.4 5.5 v hysteresis 20 80 150 mv vin shutdown supply current en1 = en2 = gnd or floating, ldo3en = gnd - 6 15 a vin standby supply current en1 = en2 = gnd or floating, ldo3en = vcc1 - 150 250 a linear regulator ldo5 output voltage i _ldo5 = 0 4.9 5.0 5.1 v i _ldo5 = 100ma (note 6) 4.9 5.0 5.1 v ldo5 short-circuit current (note 6) ldo5 = gnd - 190 - ma ldo5 uvlo threshold voltage (note 6) rising edge of ldo5 - 4.35 - v falling edge of ldo5 - 4.15 - v smps2 to ldo5 switchover threshold 4.63 4.80 4.93 v smps2 to ldo5 switchover resistance (note 6) vout2 to ldo5, vout2 = 5v - 2.5 3.2 ldo3 reference voltage (note 6) - 1.2 - v ldo3 voltage regulation range ldo3in > v ldo3 +dropout 1.2 - 5 v ldo3 short-circuit current (note 6) ldo3 = gnd - 180 - ma ldo3en input voltage rising edge 1.1 - 2.5 v falling edge 0.94 - 1.06 v ldo3en input leakage current ldo3en = gnd or vcc1 -1 1 a ldo3 discharge on-resistance ldo3en = gnd - 36 60 vcc vcc input bias current (note 6) en1 = en2 = vcc1, fb1 = fb2 = 0.65v - 2 - ma vcc1 start-up voltage en1 = en2 = ldo3en = gnd 3.45 3.6 3.75 v isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
4 fn6665.5 may 13, 2011 vcc2 por threshold rising edge 4.35 4.45 4.55 v falling edge 4.10 4.20 4.30 v pwm reference voltage (note 6) -0.6- v regulation accuracy vout regulated to 0.6v -1 - 1 % fb input bias current fb = 0.6v -10 - 30 na frequency range 200 - 600 khz frequency set accuracy (note 7) f sw = 300khz -12 - 12 % vout voltage regulation range vin > 6v for vout = 5.5v 0.6 - 5.5 v vout soft-discharge resistance - 14 50 power-good pgood pull-down impedance soft-start, i _pgood = 5ma sinking - 32 100 uvp, i _pgood = 5ma sinking - 95 200 ovp, i _pgood = 5ma sinking - 63 150 ocp, i _pgood = 5ma sinking - 32 100 pgood leakage current pgood = vcc1 - 0 1 a maximum pgood sink current (note 6) - 5 - ma pgood soft-start delay from en high to pgood high (for one smps channel) 2.20 2.75 3.70 ms en2(1) = floating, from en1(2) high to pgood2(1) high 4.50 5.60 7.50 ms gate driver ugate pull-up on-resistance (note 6) 200ma source current - 1.0 1.5 ugate source current (note 6) ugate-phase = 2.5v - 2.0 - a ugate pull-down on-resistance (note 6) 250ma source current - 1.0 1.5 ugate sink current (note 6) ugate-phase = 2.5v - 2.0 - a lgate pull-up on-resistance (note6) 250ma source current - 1.0 1.5 lgate source current (note 6) lgate-pgnd = 2.5v - 2.0 - a lgate pull-down on-resistance (note 6) 250ma source current - 0.5 0.9 lgate sink current (note 6) lgate-pgnd = 2.5v - 4.0 - a ugate to lgate deadtime (note 6) ug falling to lg rising, no load - 21 - ns lgate to ugate deadtime (note 6) lg falling to ug rising, no load - 21 - ns bootstrap diode forward voltage (note 6) 2ma forward diode current - 0.58 - v bootstrap diode reverse leakage current v r = 25v - 0.2 1 a control fccm input voltage low level (dcm enabled) - - 0.8 v float level (dcm with audio filter) 1.9 - 2.1 v high level (forced ccm) 2.4 --v fccm input leakage current fccm = gnd or vcc1 -2 - 2 a electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise noted. typical values are at t a =+25c, vin = 12v. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter conditions min (note 8) typ max (note 8) units isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
5 fn6665.5 may 13, 2011 audio filter switching frequency (note 6) fccm floating - 28 - khz en input voltage clear fault level/smps off level - - 0.8 v delay start level 1.9 - 2.1 v smps on level 2.4 --v en input leakage current en = gnd or vcc1 -3.5 - 3.5 a isen input impedance (note 6) en = vcc1 - 600 - k isen input leakage current (note 6) en = gnd - 0.1 - a protection ocset input impedance (note 6) en = vcc1 - 600 - k ocset input leakage current (note 6) en = gnd - 0.1 - a ocset current source en = vcc1 9 10.0 10.5 a ocp (v ocset -v isen ) threshold -1.75 0.0 1.75 mv uvp threshold falling edge, referenced to fb 81 84 87 % ovp threshold rising edge, referenced to fb 113 116 120 % falling edge, referenced to fb 99.5 103 106 % otp threshold (note 6) rising edge - 150 - c falling edge - 135 - c notes: 6. limits established by characterization and are not production tested. 7. f sw accuracy reflects ic tolerance only; it does not include frequency variation due to v in , v out , l out , esr cout , or other application specific parameters. 8. parameters with min and/or max limits are 100% tested at + 25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise noted. typical values are at t a =+25c, vin = 12v. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter conditions min (note 8) typ max (note 8) units isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
6 fn6665.5 may 13, 2011 typical application circuits the below typical application ci rcuits generate the 5v/8a and 3.3v/8a main supplies in a notebook computer. the input supply (vbat) range is 5.5v to 25v figure 1. typical application circuit with inductor dcr current sense figure 2. typical application circuit with resistor current sense vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 is e n 2 vout2 fb2 3.3v 5v 3.3v 5v ldo5 ldo3* vcc1 vcc2 ldo5 pgood2 pgood1 pgnd gnd en1 en2 fset1 fset2 boot1 boot2 ldo3in* ldo3fb* fccm ldo3en* 0.22f 0.22f irf7821 irf7821 irf7832 irf7832 4.7h 4.7h 9.09k 68.1k 750 1200pf 14k 14k 0.022f 100k 100k 0.01f 0.01f 19.6k 24.3k 1f 4.7f 4.7f 10k 17.4k 10k 45.3k 10 1f 330f 330f 1200pf 750 14k 14k 0.022f 4x10f *isl62381, isl62382, isl62381c, and isl62382c only isl62381 isl62382 isl62383 isl62381c isl62382c isl62383c vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 is e n 2 vout2 fb2 3.3v 5v 3.3v 5v ldo5 ldo3* vcc1 vcc2 ldo5 pgood2 pgood1 pgnd gnd en1 en2 fset1 fset2 boot1 boot2 ldo3in* ldo3fb* fccm ldo3en* 0.22f 0.22f irf7821 irf7821 irf7832 irf7832 4.7h 4.7h 4x10f 0.01f 0.01f 24.3k 19.6k 1f 1f 4.7f 4.7f 10k 17.4k 9.09k 68.1k 1200pf 1200pf 750 750 100k 100k 45.3k 10k 330f 330f 10 0.001 0.001 1k 1k 1k 1k *isl62381, isl62382, isl62381c, and isl62382c only isl62381 isl62382 isl62383 isl62381c isl62382c isl62383c isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
7 fn6665.5 may 13, 2011 typical application circuits the below typical application ci rcuits generate the 1.05v/15a and 1.5v/15a main supplies in a notebook computer. the input supply (vbat) range is 5.5v to 25v figure 3. typical application circuit with inductor dcr current sense figure 4. typical application circuit with resistor current sense vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 is e n 2 vout2 fb2 1.05v 1.5v 3.3v 5v ldo5 ldo3* vcc1 vcc2 ldo5 pgood2 pgood1 pgnd gnd en1 en2 fset1 fset2 boot1 boot2 ldo3in* ldo3fb* fccm ldo3en* vbat 0.22f 0.22f irf7821x2 irf7821x2 irf7832x2 irf7832x2 2.2h 2.2h 24.3k 36.5k 590 1800p f 16.2k 16.2k 0.022f 100k 100k 0.01f 0.01f 14k 17.4k 1f 4.7f 4.7f 10k 17.4k 48.7k 36.5k 10 1f 330fx2 330fx2 1800pf 590 16.2k 16.2k 0.022f 6x10f isl62381 *isl62381, isl62382, isl62381c, and isl62382c only isl62382 isl62383 isl62381c isl62382c isl62383c vbat vin phase1 ugate1 lgate1 ocset1 is e n 1 vout1 fb1 phase2 ugate2 lgate2 ocset2 is e n 2 vout2 fb2 1.05v 1.5v 3.3v 5v ldo5 ldo3* vcc1 vcc2 ldo5 pgood2 pgood1 pgnd gnd en1 en2 fset1 fset2 boot1 boot2 ldo3in* ldo3fb* fccm ldo3en* vbat 0.22f 0.22f irf7821x2 irf7821x2 irf7832x2 irf7832x2 2.2h 2.2h 6x10f 0.01f 0.01f 17.4k 14k 1f 1f 4.7f 4.7f 10k 17.4k 24.3k 36.5k 1800pf 1800pf 590 590 100k 100k 36.5k 48.7k 330fx2 330fx2 10 0.001 0.001 2k 2k 2k 2k *isl62381, isl62382, isl62381c and isl62382c only isl62381 isl62382 isl62383 isl62381c isl62382c isl62383c isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
8 fn6665.5 may 13, 2011 pin descriptions pin number name function 28 ld 32 ld 1 1 pgood2 smps2 open-drain power-good status output. connect to ldo5 through a 100k ? resistor. output will be high when the smps2 output is within the regulation window with no faults detected. 2 2 fset2 frequency control input for smps2. connect a resistor to ground to program the switching frequency. a small ceramic capacitor such as 10nf is necessary to pa rallel with this resistor to smooth the voltage. 3 3 fccm logic input to control efficiency mode. logic high forc es continuous conduction mode (ccm ). logic low allows full discontinuous conduction mode (dcm). float this pin for ultrasonic dcm operation. 4 4 vcc2 smps2 analog power supply input for reference voltages and currents. connect to vcc1 with a 10 resistor. bypass to ground with a 1f ceramic capacitor near the ic. 5 5 vcc1 smps1 analog power supply input for reference voltage s and currents. it is internally connected to the ldo5 output. bypass to ground with a 1f ceramic capacitor near the ic. - 6 ldo3en logic input for enabling and disabling the ldo3 linear regulator. positive logic input. 6 7 fset1 frequency control input for smps1. connect a resistor to ground to program the switching frequency. a small ceramic capacitor such as 10nf is necessary to pa rallel with this resistor to smooth the voltage. 7 8 pgood1 smps1 open-drain power-good status output. connect to ldo5 through a 100k ? resistor. output will be high when the smps1 output is within the regulation window with no faults detected. 8 9 fb1 smps1 feedback input used for output voltage programming and regulation. 9 10 vout1 smps1 output voltage sense input. used for soft-discharge. 10 11 isen1 smps1 current sense input. used for overcurrent protection and r 3 regulation. 11 12 ocset1 input from current-sensing network used to pr ogram the overcurrent shutdown threshold for smps1. 12 13 en1 logic input to enable and disable smps1. a logic high wi ll enable smps1 immediately. a logic low will disable smps1. floating this input will delay smps1 start-up until af ter smps2 achieves regulation. 13 14 phase1 smps1 switching node for high-side gate drive return and synthetic ripple modulation. connect to the switching nmos source, the synchronous nmos dr ain, and the output inductor for smps1. 14 15 ugate1 high-side nmos gate drive output for smps1. connect to the gate of the smps1 switching fet. 15 16 boot1 smps1 bootstrap input for the switching nmos gate dr ivers. connect to phase1 with a 0.22f ceramic capacitor. 16 17 lgate1 low-side nmos gate drive output for smps1. connect to the gate of the smps1 synchronous fet. - 18 ldo3fb ldo3 linear regulator feedback input us ed for output voltage programming and regulation. - 19 ldo3 ldo3 linear regulator output, providing up to 100m a. bypass to ground with a 4.7f ceramic capacitor. - 20 ldo3in power input for ldo3. must be connected to a voltage greater than the ldo3 set point plus the dropout voltage. 17 21 vin feed-forward input for line voltage transient co mpensation. connect to the power train input voltage. 18 22 ldo5 5v linear regulator output, providing up to 100ma bef ore switchover to smps2. bypass to ground with a 4.7f ceramic capacitor. 19 23 pgnd power ground for smps1 and smps2. this provides a return path for synchronous fet switching currents. 20 24 lgate2 low-side nmos gate drive output for smps2. connect to the gate of the smps2 synchronous fet. 21 25 boot2 smps2 bootstrap input for the switching nmos gate dr ivers. connect to phase2 with a 0.22f ceramic capacitor. 22 26 ugate2 high-side nmos gate drive output for smps2. connect to the gate of the smps2 switching fet. 23 27 phase2 smps2 switching node for high-side gate drive return and synthetic ripple modulation. connect to the switching nmos source, the synchronous nmos dr ain, and the output inductor for smps2. 24 28 en2 logic input to enable and disable smps2. a logic high wi ll enable smps2 immediately. a logic low will disable smps2. floating this input will delay smps2 start-up until af ter smps1 achieves regulation. 25 29 ocset2 input from current-sensing network used to pr ogram the over-current shutdown threshold for smps2. 26 30 isen2 smps2 current sense input. used for overcurrent protection and r 3 regulation. 27 31 vout2 smps2 output voltage sense input. used for soft-discharge and switchover to ldo5 output. isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
9 fn6665.5 may 13, 2011 28 32 fb2 smps2 feedback input used for output voltage programming and regulation. bottom pad bottom pad gnd analog ground of the ic. unless otherwise stated, signals are reference to this gnd. pin descriptions (continued) pin number name function 28 ld 32 ld typical performance figure 5. channel 1 efficiency at v o =3.3v, dem operation. high-side 1xirf7821, r ds(on) =9.1m ; low-side 1xirf7832, r ds(on) =4m ; l = 4.7h, dcr = 14.3m ; ccm f sw = 270khz figure 6. channel 2 efficiency at v o =5v, dem operation. high-side 1xirf7821, r ds(on) =9.1m ; low-side 1xirf7832, r ds(on) =4m ; l = 4.7h, dcr = 14.3m ; ccm f sw = 330khz figure 7. power-on, v in = 12v, load = 5a, v o =3.3v figure 8. power-off, v in = 12v, i o =5a, v o =3.3v 50 55 60 65 70 75 80 85 90 95 100 0.10 1.00 10.00 i out (a) efficiency (%) v in = 7v v in = 12v v in = 19v 50 55 60 65 70 75 80 85 90 95 100 0.01 0.10 1.00 10.00 i out (a) efficiency (%) v in = 7v v in = 12v v in = 19v v o1 fb1 pgood1 phase1 v o1 fb1 pgood1 phase1 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
10 fn6665.5 may 13, 2011 figure 9. enable control, en1 = high, v in = 12v, v o = 3.3v, i o =5a figure 10. enable control, en1 = low, v in = 12v, v o = 3.3v, i o =5a figure 11. ccm steady-state operation,v in = 12v, v o1 = 3.3v, i o1 =5a, v o2 =5v, i o2 =5a figure 12. dcm steady-state operation,v in = 12v, v o1 = 3.3v, i o1 = 0. 2a, v o2 =5v, i o2 = 0. 2a figure 13. audio filter operation, v in = 12v, v o1 = 3.3v, v o2 = 5v, no load figure 14. transient response, v in = 12v, v o =3.3v, i o = 0.1a/8.1a @ 2.5a/s typical performance (continued) v o1 fb1 pgood1 en1 v o1 fb1 pgood1 en1 phase2 v o2 phase1 v o1 v o1 phase1 v o2 phase2 v o1 phase1 v o2 phase2 i o1 v o1 phase1 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
11 fn6665.5 may 13, 2011 figure 15. load insertion response, v in =12v, v o = 3.3v, i o = 0.1a/8.1a @ 2.5a/s figure 16. load release response, v in =12v, v o = 3.3v, i o = 0.1a/8.1a @ 2.5a/s figure 17. delayed start, v in = 12v, v o1 =3.3v, v o2 =5v, en2 = float, no load figure 18. delayed start, v in =12v, v o1 =3.3v, v o2 =5v, en1 = float, no load figure 19. delayed start, v in = 12v, v o1 =3.3v, v o2 =5v, en1 = 1, en2 = float, no load figure 20. overcurrent protection, v in =12v, v o =3.3v typical performance (continued) v o1 phase1 i o1 v o1 phase1 i o1 en1 v o1 v o2 v o2 en2 v o1 v o1 pgood1 pgood2 v o2 i o1 pgood1 v o1 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
12 fn6665.5 may 13, 2011 figure 21. crowbar o vervoltage protection, v in =12v, v o = 3.3v, no load figure 22. tri-state overvoltage protection, v in = 12v, v o = 3.3v, no load typical performance (continued) pgood1 lgate1 v o1 ugate1-phase1 pgood1 lgate1 v o1 ugate1-phase1 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
13 fn6665.5 may 13, 2011 block diagram v ref 0.6v r 3 modulator fset1/2 fb1/2 ugate driver lgate driver pwm vin vout1/2 boot1/2 soft discharge ldo5 pgnd lgate1/2 phase1/2 ugate1/2 fccm 5v ldo start-up and shutdown logic en1 ldo3en* ocset1/2 isen1/2 10a ocp protection logic ovp/uvp/ocp/otp pgood1/2 v ref + 16% v ref - 16% ovp uvp fb1/2 thermal monitor 3.3v ldo ldo3* soft discharge 4.8v vout2 vcc1/2 bias and reference t-pad ldo3fb* ldo3in* * isl62381, isl2382, isl62381c and isl62382c only isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
14 fn6665.5 may 13, 2011 theory of operation four output controller the isl62381, isl62382, isl62381c and isl62382c generate four regulated output voltages, including two pwm controllers and two ldos. the two pwm channels are identical and almost entirely independent, with the exception of sharing the gnd pin. unless otherwise stated, only one individual channel is discussed, and the conclusion applies to both channels. pwm modulator the isl62381, isl62382, isl62383, isl62381c, isl62382c and isl62383c modulator features intersil?s r 3 technology, a hybrid of fixed frequency pwm control and variable frequency hysteretic control. intersil?s r 3 technology can simultaneously affect t he pwm switching frequency and pwm duty cycle in response to i nput voltage and output load transients. the r 3 modulator synthesizes an ac signal v r , which is an analog representa tion of the output inductor ripple current. t he duty-cycle of v r is the result of charge and discharge current through a ripple capacitor c r . the current through c r is provided by a transconductance amplifier g m that measures the vin and vo pin voltages. the positive slope of v r can be written as equation 1: the negative slope of v r can be written as equation 2: where g m is the gain of the transconductance amplifier. a window voltage v w is referenced with respect to the error amplifier output voltage v comp , creating an envelope into which the ripple voltage v r is compared. the amplitude of v w is set by a resistor connected across the fset and gnd pins. the v r, v comp, and v w signals feed into a window comparator in which v comp is the lower threshold voltage and v comp + v w is the higher threshold voltage. figure 23 shows pwm pulses being generated as v r traverses the v comp and v comp + v w thresholds. the pwm switching frequency is proportional to the slew rates of the positive and negative slopes of v r; it is inversely proportional to the voltage between v w and v comp. equation 3 illustrates how to calculate the window size based on output voltage and frequency set resistor r w . programming the pwm switching frequency these controllers do not use a clock signal to produce pwms. the pwm switching frequency f sw is programmed by the resistor r w that is connected from the fset pin to the gnd pin. the approxim ate pwm switching frequency can be expressed as written in equation 4: for a desired f sw , the r w can be selected by equation 5. where c r = 17pf with 20% error range. to smooth the fset pin voltage, a ceramic capacitor such as 10nf is necessary to parallel with r w. it is recommended that whenever the control loop compensation network is modified, f sw should be checked for the correct frequency and if necessary, adjust r w . power-on reset these controllers are disabled until the voltage at the vin pin has increased above the rising power-on reset (por) threshold voltage. the controller will be disabled when the voltage at the vin pin decreases below the falling por threshold. in addition to vin por, the ldo5 pin is also monitored. if its voltage falls below 4.2v, the smps outputs will be shut down. this ensures that there is sufficient boot voltage to enhance the upper mosfet. en, soft-start and pgood these controllers use a digital soft-start circuit to ramp the output voltage of each smps to the programmed regulation setpoint at a predictable slew rate. the slew rate of the soft-start sequence has been selected to limit the in-rush current through the output capacitors as they charge to the desired regulation voltage. when the en pins are pulled above their rising thresholds, the pgood soft-start delay, t ss , starts and the output voltage begins to rise. the fb pin ramps to 0.6v in approximately 1.5ms and the pgood pin goes to high impedance approxim ately 1.25ms after the fb pin voltage reaches 0.6v. v rpos g m v in v out ? () c r ? ? = (eq. 1) v rneg g m v out c r ? ? = (eq. 2) figure 23. modulator waveforms during load transient pwm ripple capacitor voltage v r error amplifier window voltage v w (wrt v comp ) voltage v comp v w g m v out 1d ? () r w ?? ? = (eq. 3) f sw 1 10 c ? r r w ? --------------------------------- = (eq. 4) r w 1 10 c ? r f sw ? ------------------------------------ = (eq. 5) isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
15 fn6665.5 may 13, 2011 the pgood pin indicates when the converter is capable of supplying regulated voltage. it is an undefined impedance if v in is not above the rising por thre shold or below the por falling threshold. when a fault is detect ed, these controllers will turn on the open-drain nmos, whic h will pull pgood low with a nominal impedance of 63 or 95 . this will flag the system that one of the output volt ages is out of regulation. separate enable pins allow for full soft-start sequencing. because low shutdown quiescent current is necessary to prolong battery life in notebook applications, the ldo5 5v ldo is held off until any of the three enable signals (en1, en2 or ldo3en) is pulled high. soft-start of all outputs will only start until after ldo5 is above the 4.2v por threshold. in addition to user-programmable sequencing, these controllers include a pre-programmed sequential smps so ft-start feature. table 1 shows the smps enable truth table. vcc1 the vcc1 nominal operation voltage is 5v. if en1, en2 and ldo3en are all logic low, the vcc1 start-up voltage is 3.6v when vin is applied on these controllers. ldo5 is held off until any of the three enable signals (en1, en2 or ldo3en) is pulled high. when ldo5 is above the 4.2v vcc1 por threshold, vcc1 will switchover to ldo5 internally. after vin is applied, the vcc1 start-up 3.6v voltage can be used as the logic high signal of any of en1, en2 and ldo3en to enable pvcc if there is no other power supply on the board. mosfet gate-drive outputs lgate and ugate these controllers have internal gate-drivers for the high-side and low-side n-channel mosfets. the low-side gate-drivers are optimized for low duty-cycle ap plications where the low-side mosfet conduction losses are dominant, requiring a low r ds(on) mosfet. the lgate pull-down resistance is small in order to clamp the gate of the mosfet below the v gs(th) at turn-off. the current transient through the gate at turn-off can be considerable because the gate charge of a low r ds(on) mosfet can be large. adaptiv e shoot-through protection prevents a gate-driver output fr om turning on until the opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 25 is extended by the additional period that the falling gate voltage stays above the 1v threshold. the typical dead-time is 21ns. the high-side gate-driver output voltage is measured across the ugate and phase pins while the low-side gat e-driver output voltage is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the ldo5 pin. the power for the ugate gate-driver is sourced from a ?boot? capacitor connected across the boot and phase pins. the boot capacitor is charged from the 5v ldo5 supply through a ?boot diode? each time the low-side mosfet turns on, pulling the phase pin low. these contro llers have int egrated boot diodes connected from the ldo5 pins to boot pins. diode emulation fccm is a logic input that cont rols the power state of these controllers. if forced high, these controllers will operate in forced continuous-conduction-mo de (ccm) over the entire load range. this will produce the best transient response to all load conditions, but will have increased light-load power loss. if fccm is forced low, these controllers will automatically operate in diode-emulation-mode (dem) at light load to optimize efficiency in the entire load range. the table 1. smps enable sequence logic en1 en2 start-up sequence 0 0 both smps outputs off simultaneously 0 float both smps outputs off simultaneously float 0 both smps outputs off simultaneously float float both smps outputs off simultaneously 0 1 smps1 off, smps2 on 1 0 smps1 on, smps2 off 1 1 both smps outputs on simultaneously float 1 smps1 enables after smps2 is in regulation 1 float smps2 enables after smps1 is in regulation figure 24. soft-start sequence for one smps vcc and ldo5 vout en pgood fb 1.5ms 2.75ms t softstart pgood delay figure 25. lgate and ugate dead-time ugate lgate 50% 50% t lgfugr t ugflgr isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
16 fn6665.5 may 13, 2011 transition is automatically achieved by detecting the load current and turning off lgate when the inductor current reaches 0a. positive-going inductor current flows from either the source of the high-side mosfet, or the drain of the low-side mosfet. negative-going inductor current flows into the drain of the low-side mosfet. when the low-side mosfet conducts positive inductor current, the phase voltage will be negative with respect to the gnd and pgnd pins. conversely, when the low-side mosfet conducts negative inductor current, the phase voltage will be positive with respect to the gnd and pgnd pins. these controllers monitor the phase voltage when the low-side mosfet is conducting inductor current to determine its direction. when the output load current is greater than or equal to ? the inductor ripple current, the inductor current is always positive, and the converter is always in ccm. these controllers minimize the conduction loss in this condition by forcing the low-side mosfet to operate as a synchronous rectifier. when the output load current is less than ? the inductor ripple current, negative inductor current occurs. sinking negative inductor current through the low-side mosfet lowers efficiency through unnecessary conduction losses. these controllers aut omatically enter dem after the phase pin has detected positive voltage and lgate was allowed to go high for eight consecutive pwm switching cycles. these controllers will turn off the low-side mosfet once the phase voltage turns positive, indicating negative inductor current. these controllers wi ll return to ccm on the following cycle after the phase pin dete cts negative voltage, indicating that the body diode of the low-side mosfet is conducting positive inductor current. efficiency can be further improved with a reduction of unnecessary switching losse s by reducing the pwm frequency. it is characteristic of the r 3 architecture for the pwm frequency to decrease while in diode emulation. the extent of the frequency redu ction is proportional to the reduction of load current. upon entering dem, the pwm frequency makes an initial step -reduction because of a 33% step-increase of the window voltage v w . because the switching frequency in dem is a function of load current, very light load conditions can produce frequencies well into the audio band. this can be problematic if audible noise is coupled into audio amplifier circuits. to prevent this from occurring, these controllers allow the user to float the fccm input. this will allow dem at light loads, but will prevent t he switching frequency from going below ~28khz to prevent noise injection into the audio band. a timer is reset each pwm pulse. if the timer exceeds 30s, lgate is turned on, causing the ramp voltage to reduce until another ugate is commanded by the voltage loop. overcurrent protection the overcurrent protection (ocp) setpoint is programmed with resistor, r ocset , that is connected across the ocset and phase pins. figure 26 shows the overcurrent-set circuit for smps1. the inductor consists of inductance l and the dc resistance (dcr). the inductor dc current i l creates a voltage drop across dcr, given by equation 6: theses controllers sink a 10a current into the ocset1 pin, creating a dc voltage drop across the resistor r ocset , given by equation 7: resistor r o is connected between the isen1 pin and the actual output of the converter. during normal operation, the isen1 pin is a high impedance path, therefore there is no voltage drop across r o . the dc voltage difference between the ocset1 pin and the isen1 pin can be established using equation 8: these controllers monitor the ocset1 pin and the isen1 pin voltages. once the ocset1 pin voltage is higher than the isen1 pin voltage for more than 10s, these controllers declare an ocp fault. the value of r ocset is then written as equation 9: where: -r ocset ( ) is the resistor used to program the overcurrent setpoint -i oc is the output current threshold that will activate the ocp circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m , the choice of r ocset is r ocset = 20a x 4.5m /10a = 9k . figure 26. overcurrent-set circuit phase1 c o l v o r ocset c sen ocset1 isen1 r o isl62381 dcr i l 10a + _ v dcr + _ v rocset v dcr i l dcr ? = (eq. 6) v rocset 10 ar ocset ? = (eq. 7) v ocset1 v ? isen1 i l dcr ? 10 ar ocset ? ? = (eq. 8) (eq. 9) r ocset i oc dcr ? 10 a --------------------------- = isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
17 fn6665.5 may 13, 2011 resistor r ocset and capacitor c sen form an rc network to sense the inductor current. to sense the inductor current correctly, not only in dc operation but also during dynamic operation, the rc network time constant r ocset c sen needs to match the inductor ti me constant l/dcr. the value of c sen is then written as equation 10: for example, if l is 1.5h, dcr is 4.5m , and r ocset is 9k , the choice of c sen = 1.5h/(9k x 4.5m ) = 0.037f . upon converter start-up, the c sen capacitor bias is 0v. to prevent false ocp during this time, a 10a current source flows out of the isen1 pin, generating a voltage drop on the r o resistor, which should be chosen to have the same resistance as r ocset . when pgood pin goes high, the isen1 pin current source will be removed. when an ocp fault is decla red, the pgood pin will pull-down to 32 and latch off the converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage, or until v in has decayed below the falling por threshold. when using a discrete current sense resistor, inductor time-constant matching is not required. equation 7 remains unchanged, but equation 8 is modified in equation 11: furthermore, equation 9 is changed in equation 12: where r sense is the series power resistor for sensing inductor current. for example, with an r sense = 1m and an ocp target of 10a, r ocset = 1k . overvoltage protection the ovp fault detection circuit triggers after the fb pin voltage is above the rising overvoltage threshold for more than 2s. the fb pin voltage is 0.6v in normal operation. the rising over voltage threshold is typically 116% of that value, or 1.16*0.6v = 0.696v. when an ovp fault is declared, the pgood pin will pull down with 65 and latch-off the converter. the ovp fault will remain latched until the en pin has been pulled below the falling en threshold voltage, or until v in has decayed below the falling por threshold. for isl62381, isl62381c, isl62383 and isl62383c, although the converter has latched-off in response to an ovp fault, the lgate gate-driver output will retain the ability to toggle the low-side mosfet on and off in response to the output voltage transversing the ovp rising and falling thresholds. the lgate gate-driver will turn on the low-side mosfet to discharge the output voltage, thus protecting the load from potentially damaging voltage levels. the lgate gate-driver will turn off the low-side mosfet once the fb pin voltage is lower than the falling overvoltage threshold for more than 2s. the falling overvoltage threshold is typically 106% of the reference voltage, or 1.06*0.6v = 0.636v. this process repeats as long as the output voltage fault is present, allowing the isl62381, isl62381c, isl62383 and isl62383c to protect against persistent overvoltage conditions. for isl62382 and isl62382c, if ov p is detected, it simply tri- states the phase node by turning ugate and lgate off. undervoltage protection the uvp fault detection circuit triggers after the fb pin voltage is below the undervoltage threshold for more than 2s. the undervoltage threshold is typically 86% of the reference voltage, or 0.86*0.6v = 0.516v. if a uvp fault is declared, and the pgood pin will pull-down with 93 and latch-off the converter. the fault will remain latched until the en pin has been pulled below the falling enable threshold, or if v in has decayed below the falling por threshold. programming the output voltage when the converter is in regul ation, there will be 0.6v between the fb and gnd pins. connect a two-resistor voltage divider across the out and gnd pins with the output node connected to the fb pin, as shown in figure 27. scale the voltage-divider network such that the fb pin is 0.6v with respect to the gnd pin when the converter is regulating at the desired out put voltage. the output voltage can be programmed from 0.6v to 5.5v. programming the output volta ge is written as equation 13: where: -v out is the desired output voltage of the converter - the voltage to which the converter regulates the fb pin is the v ref (0.6v) -r top is the voltage-programming resistor that connects from the fb pin to the converter output. in addition to setting the output voltage, this resistor is part of the loop compensation network -r bottom is the voltage-programming resistor that connects from the fb pin to the gnd pin choose r top first when compensati ng the control loop, and then calculate r bottom according to equation 14: compensation design figure 27 shows the recommended type-ii compensation circuit. the fb pin is the inverting input of the error amplifier. the comp signal, the output of the error amplifier, is inside the chip and unavailable to users. c int is a 100pf capacitor (eq. 10) c sen l r ocset dcr ? ----------------------------------------- = v ocset1 v ? isen1 i l r sense ? 10 ar ocset ? ? = (eq. 11) r ocset i oc r sense ? 10 a ------------------------------------- = (eq. 12) v out v ref 1 r top r bottom ---------------------------- - + ?? ?? ?? ? = (eq. 13) r bottom v ref r ? top v out v ref ? ------------------------------------- = (eq. 14) isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
18 fn6665.5 may 13, 2011 integrated inside the ic that connects across the fb pin and the comp signal. r top , r fb , c fb and c int form the type-ii compensator. the frequency domain transfer function is given by equation 15: the lc output filter has a double pole at its resonant frequency that causes rapid phase change. the r 3 modulator used in these controllers make the lc out put filter resemble a first order system in which the closed loop stability can be achieved with the recommended type-ii compensation network. intersil provides a pc-based tool (example page is shown later) that can be used to calculate compensation network component values and help simulate the loop frequency response. ldo5 linear regulator in addition to the two smps outputs, these controllers also provide two linear regulator outputs. ldo5 is fixed 5v ldo output capable of sourcing 100ma continuous current. when the output of smps2 is programmed to 5v, smps2 will automatically take over the load of ldo5. this provides a large power savings and boosts the efficiency. after switchover to smps2, the ldo5 output current plus the mosfet drive current should not exceed 100ma in order to guarantee the ldo5 output voltage in the range of 5v 5%. the total mosfet drive current can be estimated by equation 16. where q g is the total gate charge of all the power mosfet in two smps regulators. then the ldo5 output load current should be less than 100ma-i drive . ldo3 linear regulator isl62381, isl62381c, isl62382 and isl62382c include ldo3 linear regulator whose output is adjustable from 1.2v to 5v through ldo3fb pin with a 1.2v reference voltage. it can be independently enabled from both smps channels. logic high of ldo3en will enable ldo3. ldo3 is capable of sourcing 100ma continuous current and draws its power from ldo3in pin, which must be connected to a voltage greater than the ldo3 output voltage pl us the dropout voltage. currents in excess of the limit will cause the ldo3 voltage to drop dramatically, limitin g the power dissipation. thermal monitor and protection ldo3 and ldo5 can dissipate non-trivial power inside these controllers at high input-to-output voltage ratios and full load conditions. to protect the silic on, these controllers continually monitor the die temperature. if the temperature exceeds +150c, all outputs will be turned off to sharply curtail power dissipation. the outputs will remain off until the junction temperature has fallen below +135c. general application design guide this design guide is intended to provide a high-level explanation of the steps neces sary to design a single-phase power converter. it is assumed th at the reader is familiar with many of the basic skills and te chniques referenced in the following section. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck c onverter is a function of the input and the output voltage. this relationship is written as equation 17: the output inductor peak-to-peak ripple current is written as equation 18: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several criteria such as mosfet switching loss, inducto r core loss, and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated by equation 19: where i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another fa ctor to consider when choosing the inductor is its saturation characteristics at elevated temperatures. a saturated induct or could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops out of the capacitor. these two voltages are written as equation 20: and equation 21: (eq. 15) g comp s () 1sr top r fb + () c ? fb ? + sr top c int 1sr fb c ? fb ? + () ? ? ? ------------------------------------------------------------------------------------------- = isl6238 r bottom ea + fb c int = 100pf - ref vo figure 27. compensation reference circuit r top r fb c fb comp (eq. 16) i drive q g f sw ? = d v out v in --------------- = (eq. 17) (eq. 18) i pp v out 1d ? () ? f sw l ? ------------------------------------- - = (eq. 19) p copper i load 2 dcr ? = v esr i pp e ? sr = (eq. 20) isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
19 fn6665.5 may 13, 2011 if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors should be considered in this scenario. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current requir ed by the switching circuit. their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. figure 28 is a graph of the input capacitor rms ripple current, normalized relative to output load current, as a function of duty cycle and is adjusted for converter efficiency. the nor malized rms ripple current calculation is written as equation 22: where: -i max is the maximum continuous i load of the converter - k is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as: in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. mosfet selection and considerations typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the mosfet switches off. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. unlike the lo w-side mosfet which has the drain-source voltage clamped by its body diode during turn off, the high-side mosfet turns off with a v ds of approximately v in - v out , plus the spike across it. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. it should be noted that this is an optimal configuration of mosfet selection for low duty cycle ap plications (d < 50%). for higher output, low input voltage solutions, a more balanced mosfet selection for high- and low-side devices may be warranted. for the low-side (ls) mosfet, the power loss can be assumed to be conductive only and is written as equation 24: for the high-side (hs) mosfet, the its conduction loss is written as equation 25: for the high-side mosfet, the switching loss is written as equation 26: v c i pp 8c o f ? sw ? ------------------------------- = (eq. 21) (eq. 22) i c in rms normalized , () i max d1d ? () ? dk 2 ? 12 -------------- + ? i max ----------------------------------------------------------------------- = d v out v in eff ? -------------------------- = (eq. 23) figure 28. normalized rms input current @ eff = 1 normalized input rms ripple current duty cycle 00.1 0.2 0.30.4 0.60.7 0.80.9 1.0 0.5 0 0.12 0.24 0.36 0.48 0.6 k = 1 k = 0.75 k = 0.5 k = 0.25 k = 0 (eq. 24) p con_ls i load 2 r ? ds on () _ls 1d ? () ? (eq. 25) p con_hs i load 2 r ? ds on () _hs d ? = (eq. 26) p sw_hs v in i valley t on f ? sw ? ? 2 ---------------------------------------------------------------- - v in i peak t off f ? sw ? ? 2 ------------------------------------------------------------- + = isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
20 fn6665.5 may 13, 2011 where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off selecting the bootstrap capacitor the selection of the bootstrap capacitor is written as equation 27: where: -q g is the total gate charge required to turn on the high-side mosfet - v boot , is the maximum allowed voltage decay across the boot capacitor each time the high-side mosfet is switched on as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacitance. in this example, 0.22f will suffice. use an x7r or x5r ceramic capacitor. layout considerations as a general rule, power should be on the bottom layer of the pcb and weak analog or logic signals are on the top layer of the pcb. the ground-pl ane layer should be adjacent to the top layer to provide shielding. the ground plane layer should have an island located under the ic, the compensation components, and the fset components. the island should be connected to the rest of the ground plane layer at one point. because there are two smps outputs and only one pgnd pin, the power train of both channels should be laid out symmetrically. the line of bilateral symmetry should be drawn through pins 4 and 21 (pins 4 and 18 for isl62383). this layout approach ensures that the controller does not favor one channel over another during critical switching decisions. figure 30 illustrates one example of how to achieve proper bilateral symmetry. signal ground and power ground the bottom of these controllers tqfn package is the signal ground (gnd) terminal for analog and logic signals of the ic. connect the gnd pad of these controllers to the island of ground plane under the top layer using several vias for a robust thermal and electrical conduction path. connect the input capacitors, the output capa citors, and the source of the lower mosfets to the powe r ground (pgnd) plane. the following pin descriptions use isl62381 as an example. pgnd (pin 23) this is the return path for the pull-down of the lgate low-side mosfet gate driver. ideally, pgnd should be connected to the source of the low-side mosfet with a low-resistance, low- inductance path. vin (pin 21) the vin pin should be connected close to the drain of the high-side mosfet, using a low resistance and low inductance path. vcc (pins 4 and 5) for best performance, place the decoupling capacitor very close to the vcc and gnd pins. ldo5 (pin 22) for best performance, place the decoupling capacitor very close to the ldo5 and respective pgnd pin, preferably on the same side of the pcb as the isl62381 ic. en (pins 13 and 28) and pgood (pins 1 and 8) these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. ocset (pins 12 and 29) and isen (pins 11 and 30) for dcr current sensing, curr ent-sense network, consisting of r ocset and c sen , needs to be connected to the inductor pads for accurate measurement. connect r ocset to the phase-node side pad of the inductor, and connect c boot q g v boot ----------------------- - = (eq. 27) inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets figure 29. typical power component placement output capacitors schottky diode low-side mosfets input capacitors vias to ground plane inductor high-side mosfets line of symmetry pin 4 (vcc2) pin 21 (vin) l2 ci co l1 ci co u2 l2 u1 l1 isl62381 and isl62382 pgnd plane phase planes vout planes vin plane figure 30. symmetric layout guide isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
21 fn6665.5 may 13, 2011 c sen to the output side pad of the inductor. the isen resistor should also be connect ed to the output pad of the inductor with a separate trace. connect the ocset pin to the common node of node of r ocset and c sen . for resistive current sensing, connect r ocset from the ocset pin to the inductor side of the resistor pad. the isen resistor should be connected to the v out side of the resistor pad. in both current-sense configurations, the resistor and capacitor sensing elements, with the exclusion of the current sense power resistor, should be placed near the corresponding ic pin. the trace connections to the inductor or sensing resistor should be treated as kelvin connections. fb (pins 9 and 32), and vout (pins 10 and 31) the vout pin is used to generate the r 3 synthetic ramp voltage and for soft-discharge of the output voltage during shutdown events. this signal should be routed as close to the regulation point as possible. the input impedance of the fb pin is high, so place the voltage programming and loop compensation components close to the vout, fb, and gnd pins keeping the high impedance trace short. fset (pins 2 and 7) these pins require a quiet environment. the resistor r fset and capacitor c fset should be placed directly adjacent to these pins. keep fast moving nodes away from these pins. lgate (pins 17 and 24) the signal going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. route these traces in pa rallel with the trace from the pgnd pin. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in proximity with these traces on any layer. boot (pins 16 and 25), ugate (pins 15 and 26), and phase (pins 14 and 27) the signals going through thes e traces are both high dv/dt and high di/dt, with high peak charging and discharging current. route the ugate and phase pins in parallel with short and wide traces. there should be no other weak signal traces in proximity with these traces on any layer. copper size for the phase node the parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. it is best to limit the size of th e phase node copper in strict accordance with the current and thermal management of the application. an mlcc should be connected directly across the drain of the upper mosfet and the source of the lower mosfet to suppress the turn-off voltage spike. isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c
22 fn6665.5 may 13, 2011 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c package outline drawing l28.4x4 28 lead thin quad flat no-lead plastic package rev 0, 9/06 typical recommended land pattern detail "x" top view bottom view notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to amse y14.5m-1994 . 4. bottom side pin#1 id is diepad chamfer as shown. 5. tiebar shown (if present) is a non-functional feature. pin 1 index area 4 . 00 0 ~ 0 . 05 5 0 . 10 pin #1 index area chamfer 0 . 400 x 45 2 . 50 2 . 50 3 . 20 a package boundary 4 . 00 0 . 40 0 . 20 0 . 05 0 . 40 0 . 20 ref 0 . 00 - 0 . 05 see detail x'' seating plane (28x 0 . 60) (0 . 40) (28x 0 . 20) (2 . 50) (2 . 50) (3 . 20) (3 . 20) 0 . 4 x 6 = 2.40 ref 3 . 20 0 . 4 x 6 = 2 . 40 ref max. 0 . 80 (0 . 40) b side view c c 0 . 20 ref 0 . 08 c 0 . 10 c 0 . 10 m c a b 2x 14 8 7 1 28 22 21 15
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6665.5 may 13, 2011 isl62381, isl62382, isl62383, is l62381c, isl62382c, isl62383c thin quad flat no-lead plastic package (tqfn) thin micro lead frame pl astic package (tmlfp) index d/2 d e/2 e a b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 section "c-c" nx b a1 2x c 0.15 0.15 2x b ref. (nd-1)xe (ne-1)xe ref. 5 a1 a c c a3 d2 d2 e2 e2/2 side view top view 7 bottom view 7 5 2 nx k nx b 8 nx l 8 8 area 0.10 c / / (datum b) (datum a) area index 6 area n l32.5x5a 32 lead thin quad flat no-lead plastic package (compliant to jedec mo-220wjjd-1 issue c) symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.18 0.25 0.30 5, 8 d 5.00 bsc - d2 3.30 3.45 3.55 7, 8 e 5.00 bsc - e1 5.75 bsc 9 e2 3.30 3.45 3.55 7, 8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n322 nd 8 3 ne 8 3 rev. 2 05/06 notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389.

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